View source for BCR TTL SERIAL HACK



== What is this all about? ==

External serial bidirectional communication on the Model 100 today is limited to (1) the RS-232 port and (2) the modem port, both of which use the single UART in the computer.

This hacks shown here enable the BCR port to send and receive half duplex serial TTL signals.  The BCR port is already set up for TTL receive function as this is used for the Bar Code Reader function.  So these hacks provides facility to transmit as well.  In addition I provide some software routines that demonstrate the capability.

There are 2 modifications described.  I recommend the oroginal hack, as it works with both 8085 processors and is integrated into both CP/M and VT100 driver.  

For CP/M users that have an NSC800 processor installed (I think I am the only one in the world!), a patch is available which can be applied to CPM410/210 to update the CASS functionality to use the NSC800 specific BCR Hack.

BCR port serial TTL is supported in Model 100 CP/M as well as with the MVT100 Driver, for use with MVT100 Terminal or other VT100 CRT solution.

Get in touch with me at Twospruces at --the google mail service.

== Acknowledgements ==

I would like to acknowledge and thank those that have contributed to the project:

'''Philip Avery''' - for efforts with CP/M and attached Video using the MVT100 Adapter



==BCR Hack==

This the original BCR hack, and is supported in both CP/M and VT100 driver.
This is also the focus of the "VT100 function" in development on REX# / REXCPM.

===Status===
* currently supported in CPM210/410 as CASS video option
* supported in Version 2 REX#/REXCPM
* well tested

=== Supported Models ===
*  TRS-80 Model 100
*  a hardware hack for T102 is likely however not explored at this time
*  a similar hack should be possible for all ModelT versions.



=== The V1 Hardware Modification ===

quick hint- use V2!

====M100====

The core of the modification is to connect pin 3 of the BCR port to the SOD output of the CPU.  This is accomplished by adding a single wire to the PCB.

   This page details the hardware change required to transmit at 57600 baud with minimal changes.
   It can be demonstrated that, in the M100, both serial Tx and Rx is possible at 57600 over the BCR port.

   Tx and Rx at higher speeds is more challenging.  Tx speeds of up to 128000 baud have been demonstrated.
   Transmission at this rate requires disconnection of the cassette port Tx filter at C63.
   If you remove C63 you get better signal quality for TTL serial, but the cassette port is no longer usable.
   If, like me, you never use the cassette port they it may not be a big deal.

The following image shows the modification to the M100 Cassette/BCR port circuitry.

[[Image:ckt2.png||center]]<br/>

Here we see a strap added from pin 12 of M34 to pin 3 of the BCR port, defining this pin as Tx data.

The following image shows the placement of the strap on the secondary side of the M100 PCB.


[[Image:layout2.png||center]]<br/>

====T102====

    Notes:
    Hack is basically the same, with 2 differences.
    (1) You need to add a ground wire between pins 5 and 7 on the BCR port.
    (2) Connect from M34 pin 2 (not pin 12) to pin 3 of the BCR port.

== The V2 BCR Hack ==

This hack is a variant that I use for NSC800 based M100, and CP/M.
It's great because it actually works for either processor, making it more generic.

Basically this hack is only useful with NSC800, and it was needed because the NSC800 does not support SIM instruction, so there is no SOD pin.
Documented here for completion, but I don't think now that it should be mainstream, because the original hack is slightly simpler to do, and is already supported with VT100 and CP/M.

   '''Note'''
   This hack happens to work on both NSC800 and 80C85.
   But, it is slightly more work to implement, and CP/M already leverages the original Hack.
   And, no one in the world other than me is using the NSC800 ;).


===Status===
* CP/M: currently supported in CPM210/410 as CASS video option (via patch from me)
* tested and working well


=== Supported Models ===
*  TRS-80 Model 100
*  Tandy 102

=== The V2 Hardware Modification ===

This improved implementation is more universal.  SOD pin is available on 80C85 but not Z80.  The original modification therefore cannot work on NSC800.  By utilizing the /REMOTE signal on the CASSETTE port, we can accomplish the same thing...making this hack usable with both NSC800 and 80C85 processors.

The core of the modification is to connect pin 3 of the BCR port to the REMOTE signal.  This is accomplished by adding a single wire to the PCB.  Also, we want to maintain functionality of /REMOTE for cassette use.  To prevent the cassette relay from toggling as the rapid serial data is transmitted, an single capacitor is added to eliminate the high speed signals, while still enabling /REMOTE to control the cassette motor.

   This page details the hardware change required to transmit at 57600 baud with minimal changes.
   It can be demonstrated that, in the M100, both serial Tx and Rx is possible at 57600 over the BCR port.

The following image shows the modification to the M100 Cassette/BCR port circuitry.

[[Image:ckt_hack2.png||center]]<br/>

Here we see a strap added from pin 3 of M34 to pin 3 of the BCR port, defining this pin as Tx data.  Also, a single capacitor to ground is added to the base of T6, to remove AC from the /REMOTE signal.  
I recommend a surface mount 68 uF tantalum capacitor, but other similar capacitors can work.  If you hear the relay buzzing, you need a larger capacitor. ;)

The following image shows the placement of the strap and capacitor on the secondary side of the M100 PCB.


[[Image:layout_hack2.png||center]]<br/>

== Example software for sending and receiving data ==

As mentioned, the use of the BCR port to send TTL data to the external CRT is supported in Model 100 CP/M, as well as by using the VT100 Driver, which integrates the external CRT with BASIC, based on Microsoft Disk BASIC for the Model 100.

Additionally, I include some code here as examples.

   Note:
   The BCR Hack solution for TTL serial is a bit-banger, not a full UART.
   The processor is dedicated to either Tx, or Rx.
   Simultaneous Tx and Rx is not possible.
   Some software layer flow control would be needed for real communication.



=== 57600 Baud Tx/Rx Routines for 80C85 and the original V1 BCR Hack circuit ===

Currently both CP/M and my own VT100 driver uses 57600, and employsthe modification posted here.

The following code can be compiled, and run in Model 100 to demonstrate transmission between 2 machines at 57600.

Tx routine:
    [[Media:keysnd_57600.zip|keysnd_57600.asm]]
Rx routine:
    [[Media:bcrx_57600.zip|bcrx_57600.asm]]


I may have done the M100 <--> M100 testing using an improved circuit (IE remove C63).  I'm not sure; if you do try this experiment keep it in mind that the Tx signal quality is better if you pull C63.  This of course makes the cassette port useless.



==== Higher speed Tx Routines ====

Faster transmission is possible; both 115600 and 128000 baud have been demonstrated.  The core Tx routines are provided here.  Can the Rx function run faster than 57600?  A bit more on that below.

These routines are tested and work for sending a byte at the rate stated (again for V1 hack).

for Tx at 57600 baud:
    [[Media:bcrtx_57600.zip|bcrtx_57600.asm]]
for Tx at 115600 baud:
    [[Media:bcrtx_115600.zip|bcrtx_115600.asm]]
for Tx at 128000 baud:
    [[Media:bcrtx_128000.zip|bcrtx_128000.asm]]

=== 57600 Baud Tx Routine for NSC800 and 80C85 with the V2 BCR Hack ===

The following code has been used to patch CP/M, when using NSC800 processor and the associated V2 BCR hack.
This code uses only 8080 opcodes, so it runs on either processor, actually.
The timing is subtly different, but it manages to "just work".

    [[Media:keysnd_routine_v3.zip|keysnd_routine_v3.zip]]

I did not develop a specific Rx routine for use with NSC800.



=== Timing for 57600 Baud ===

Since the processor is 100% busy reading in bits during Rx functions, the requirement for the BCR port receiver is to read and place the byte into memory before the stop bit is completed.  The faster the Rx can process the received byte, the faster the link rate can be.  At 57600 baud that is about 17 microseconds.  Typical processor instruction time is between 1.2 and 1.6 microseconds, so this is about 10-12 instructions max (42.65 clock cycles).
I think that is enough time to write to memory and increment a counter or a parity, and a jump or 2.
57600 baud then looks feasible, even for large memory transfers so long as the buffer can be continuously written to without interruption while the PC is sending data.  It also means that the RS-232 port could run flat-out at 5.7 kBytes/sec in the Rx direction.
In the Tx direction it similar, but it takes a small amount of time to prepare the data before sending the start bit and following data bits.  I think it is probably better than 5.5 kbytes/sec.

For CP/M and REXCPM backup/restore this means
   4MB backup restore time could be about 12 minutes @57600 baud
    -- assuming "large packet support" on LaddieAlpha, and direct writes to block RAM.


What about 115600 or 128000 baud?  While the Tx side has been shown to work, the Rx side is the challenge. 
Challenge 1.  The M100 ROM requires an initial interrupt and then 3 jumps to get to the RST6.5 hook.  The M100 has to make it to the RX code before the data arrives.  This places a practical limit of 57600 on the rate.  76800 is too fast.  However if an option ROM was used this could potentially be sped up.

A quick look at BCRX.ASM above suggests the RX bit reception time could be reduced to 29 clock cycles, supporting ~85000 baud.




[[Category:Model T Hardware]]


[[Category:Model T Video]]